N phases of divide-by-N clocks with a 1/N duty ratio may be utilized to serialize N bits of parallel data into a serial data stream using a multiplexer. One method of generating N phases of divide-by-N clocks with a 1/N duty ratio is to use an N-bit ring counter, illustrated for a divide-by-5 implementation in FIG. 4. The 5-bit ring counter 500 is implemented by a series of five flip-flops with synchronous preset and reset. Upon reset, one of the flip-flops is synchronously preset (the first flip-flop in the series, in the example shown) and the remaining flip-flops are synchronously reset, thereby generating a token of a single “1”. This token is passed around the ring indefinitely, yielding 5 phases of divide-by-5 clocks each with a 1/5 duty ratio.
One disadvantage of this method is that when the invalid or fault states occur, the fault states are also passed around the ring indefinitely, such that invalid state detection is required. Fault states can be classified into two types: all zeros and multiple ones. Fault states due to multiple ones may be further classified into two types: two consecutive ones (e.g., 11XXX, where “X” stands for “don't care”) and one followed by another one with delay (e.g., 1X1XX). The 5 valid states and 27 invalid states for a divide-by-5 clock frequency divider with 1/5 duty ratio are illustrated in FIGS. 5A and 5B, respectively. Accordingly, combinational logic gates may be used for fault state detection, with three combinational AND gates and an OR gate used to detect all three cases and flag a fault state, as illustrated in FIG. 6.
The drawback to combinational logic fault state detection is that the circuitry typically introduces large and unbalanced load capacitances, which in turn may cause the phases to overlap and the duty ratio to deviate from 1/N at high operating frequencies.
There is, therefore, a need in the art for improved fault state detection in a clock frequency divider based on a ring counter.